The present invention relates to a semiconductor device comprising a superconductor damascene interconnect, and a method of manufacturing the semiconductor device. The invention has particular applicability in manufacturing high density semiconductor devices with deep submicron design features which require low RLC delay interconnections between active devices.
Current demands for high density and performance associated with ultra large scale integration (ULSI) require submicron features of significantly less than 0.25 microns, increased transistor and circuit speeds and improved reliability. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. This trend toward reduced feature sizes imposes severe demands on many aspects of IC fabrication, including interconnect formation. In the manufacture of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. The connections are commonly referred to as interconnects. Narrower interconnects have reduced cross-sectional area, which results in a higher interconnect resistance for a given interconnect material. This interconnect resistance, along with the capacitance of the interconnect with respect to ground and other interconnects, contributes to an RLC (resistive-inductive-capacitive) time constant which characterizes delays associated with propagation along the interconnect line. Fabrication of a circuit with increased RLC time constants lowers the speed at which the circuit can operate by increasing the time needed, for example, for a circuit output voltage to respond to a change in input voltage. Although there are other parasitic resistances and capacitances in an integrated circuit, such as those associated with the transistors themselves, in modem circuits having submicron feature sizes interconnects may contribute as much as 80% of the total circuit delay time. The increased interconnect resistance described above places a limit on how narrow interconnect lines can be and maintain tolerable interconnect resistance. The greater the resistivity of the interconnect material, the wider the lines must be, as discussed further below. As feature size decreases and transistor density increases, multiple layers of interconnect must be used to connect the transistors to each other and to the terminals of the integrated circuit. The limitation discussed above on the narrowness of interconnect lines can exacerbate this need for multiple interconnect layers. Fabrication of each interconnect layer requires deposition and patterning processes, adding to the expense of the circuit and increasing the opportunity for defect incorporation and the resulting yield reduction. It is therefore desirable to minimize the number of interconnect layers required.
Lowering the resistivity of the interconnect material alleviates many of the interconnect-related problems discussed above. Resistance, R, along the length of a structure formed from a given material is related to the resistivity, xcfx81, of the material by R=xcfx81l/A, where 1 is the length of the structure and A is its cross-sectional area. It can therefore be seen that lowering the resistivity of an interconnect material reduces the resistance of an interconnect line of a given cross-sectional area. Furthermore, a line formed from a lower-resistivity material could be made narrower before an unacceptable resistance level is reached than a line formed from a higher-resistivity material. This ability to form narrower lines may allow fewer interconnect levels to be used to form the required connections for an IC, thereby reducing costs and potentially increasing the yield of correctly-functioning circuits.
Advantages such as those described above of low-resistivity interconnect materials have driven a movement in the semiconductor industry toward replacing aluminum interconnects with interconnects made from copper. The resistivity of pure copper (about 1.7xcexcxcexa9xc2x7cm) is significantly lower than that of pure aluminum (about 2.6xcexcxcexa9xc2x7cm). Both aluminum and copper interconnects typically contain small concentrations of other elements to improve interconnect reliability. These added elements increase the resistivity of the metal, but practical copper interconnects still have resistivities up to 40% lower than those of practical aluminum interconnects. Copper interconnects can therefore be made narrower than aluminum interconnects for a given value of interconnect resistance. This may result in fewer levels of metallization being needed with copper interconnects. For a given interconnect cross-sectional area, copper interconnects exhibit lower resistances, and therefore shorter interconnect-related delays, than do aluminum interconnects.
Because copper is more difficult to etch than aluminum, in addition to difficulties in etching narrow features in metals in general as compared to etching of insulators, copper interconnects are generally formed by a damascene process.
In one connection process, which is called a xe2x80x9cdual damascenexe2x80x9d technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical xe2x80x9cviaxe2x80x9d at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channel and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
Improvements in circuit speed gained by moving from aluminum to copper have been quite beneficial as circuit speeds have increased by moving the working frequency into the range of about 1 GHz. However, development of integrated circuits having a working frequency in the range from 5 to 50 GHz requires even lower RLC delay interconnections than can be provided by copper. Thus, there exists a need semiconductor devices having interconnections having an RLC delay significantly lower than that provided by copper.
The present invention relates to a superconducting damascene interconnect structure for a semiconductor device, and to a method for fabricating the superconducting damascene interconnect structure. Thus, the present invention solves the problem of providing a significantly reduced RLC delay interconnection by replacing the conventional damascene interconnect materials with a superconductor. In addition, the present invention relates to a method of fabricating the superconducting damascene interconnect structure by a series of steps which are simple and conventional, but which avoid known problems associated with formation of damascene interconnects.
Thus, the present invention provides a method of forming a superconducting damascene interconnect structure, including:
forming a cavity in an interlevel dielectric;
forming a barrier layer in the cavity;
forming a seed layer in the cavity over the barrier layer;
filling the cavity by electrodepositing a Yxe2x80x94Baxe2x80x94Cu alloy; and
annealing in oxygen flow to form a Yxe2x80x94Baxe2x80x94Cuxe2x80x94O superconductor on the barrier layer. In one embodiment, the Yxe2x80x94Baxe2x80x94Cuxe2x80x94O superconductor has a formula YBa2Cu3O7-x, wherein xxe2x89xa60.5.
In another embodiment, the present invention relates to a method of forming a superconducting damascene interconnect structure, including:
forming a cavity in an interlevel dielectric;
forming a Yxe2x80x94Baxe2x80x94Cu alloy layer in the cavity;
forming a seed layer in the cavity over the Yxe2x80x94Baxe2x80x94Cu alloy layer;
filling the cavity by electrodepositing a Yxe2x80x94Baxe2x80x94Cu alloy fill; and
annealing in oxygen flow to form a Yxe2x80x94Baxe2x80x94Cuxe2x80x94O superconductor on the dielectric.
In another embodiment, the present invention relates to a damascene interconnect in a semiconductor device, including a Yxe2x80x94Baxe2x80x94Cuxe2x80x94O superconductor formed in a cavity in a dielectric material. In one embodiment, the Yxe2x80x94Baxe2x80x94Cuxe2x80x94O superconductor has a formula YBa2Cu3O7-x, wherein xxe2x89xa60.5.
Thus, the present invention provides a solution to the problem of providing semiconductor devices having interconnections having an RLC delay significantly lower than that provided by copper. The present invention provides a method for making a device, and a device, having a working frequency in the range from 5 to 50 GHz, which results in lower RLC delay interconnections than can be provided by copper.